E-trace for risc-v

https://blogs.sw.siemens.com/tessent/2023/11/01/debugging-risc-v-processors-using-e-trace
/riscv-trace-spec-asciidoc.pdf

branch trace

间接跳转指令（如jr指令，pc跳转到寄存器的值），中断和异常 被称为不可推断的程序计数器中断 （uninferable program counter discontinue）。是指程序计数器的变化量无法仅从程序二进制文件确定，需要报告目标地址的情况。需要使用带地址的branch包

Branch trace is also known as Instruction Delta Tracing

decoder能看到程序的二进制文件，不能知道中断在指令流中的哪里发生，trace必须报告程序流停止的地址和目的地址的指示

Most notably,
floating point exceptions and disabled interrupts do not trap.If an exception or interrupt doesn’t trap,
the program counter does not change. So, there is no need to trace all exceptions/interrupts, just traps.
In this document, interrupts and exceptions are only traced when they cause traps to be taken.

trap: the transfer of control to a trap handler caused by either an exception or an interrupt

discontinuity: another name for ’delta’